`include "define.sv"

module top_wrapper (
    // AXI全局信号
    input  wire         ACLK,
    input  wire         ARESETN,
    // AXI写地址通道
    input  wire [31:0]  AWADDR,
    input  wire [7:0]   AWLEN,
    input  wire [2:0]   AWSIZE,
    input  wire [1:0]   AWBURST,
    input  wire         AWVALID,
    output wire         AWREADY,
    // AXI写数据通道
    input  wire [31:0]  WDATA,
    input  wire [3:0]   WSTRB,
    input  wire         WLAST,
    input  wire         WVALID,
    output wire         WREADY,
    // AXI写响应通道
    output wire [1:0]   BRESP,
    output wire         BVALID,
    input  wire         BREADY,
    // APB配置接口
    input  wire         PCLK,
    input  wire         PRESETn,
    input  wire [31:0]  PADDR,
    input  wire         PWRITE,
    input  wire [31:0]  PWDATA,
    input  wire         PENABLE,
    input  wire         PSEL,
    output wire [31:0]  PRDATA,
    output wire         PREADY,
    output wire         PSLVERR
);

// 内部信号声明
wire [31:0] ram_dout;
wire        burst_done;
wire [1:0]  matrix_type;
wire [1:0]  data_type;
wire        mix_precision;
wire        axi_start;
wire [9:0]  axi_write_addr;
wire [31:0] axi_write_data;
wire        axi_write_valid;
wire        axi_done;
wire [31:0] c_out_muxed;

// top模块实例化
top u_top (
    .ACLK(ACLK),
    .ARESETN(ARESETN),
    .AWADDR(AWADDR),
    .AWLEN(AWLEN),
    .AWSIZE(AWSIZE),
    .AWBURST(AWBURST),
    .AWVALID(AWVALID),
    .AWREADY(AWREADY),
    .WDATA(WDATA),
    .WSTRB(WSTRB),
    .WLAST(WLAST),
    .WVALID(WVALID),
    .WREADY(WREADY),
    .BRESP(BRESP),
    .BVALID(BVALID),
    .BREADY(BREADY),
    .PCLK(PCLK),
    .PRESETn(PRESETn),
    .PADDR(PADDR),
    .PWRITE(PWRITE),
    .PWDATA(PWDATA),
    .PENABLE(PENABLE),
    .PSEL(PSEL),
    .PRDATA(PRDATA),
    .PREADY(PREADY),
    .PSLVERR(PSLVERR),
    .ram_dout(ram_dout),
    .burst_done(burst_done),
    .matrix_type(matrix_type),
    .data_type(data_type),
    .mix_precision(mix_precision),
    .axi_start(axi_start),
    .axi_write_addr(axi_write_addr),
    .axi_write_data(axi_write_data),
    .axi_write_valid(axi_write_valid),
    .axi_done(axi_done)
);

// 结果RAM实例化
ram_32x1024_burst u_result_ram (
    .clk(ACLK),
    .rst_n(ARESETN),
    .we(axi_write_valid & WREADY),
    .burst_en(1'b0),
    .addr(axi_write_addr),
    .din(axi_write_data),
    .burst_len(8'd0),
    .dout(),
    .burst_done()
);

endmodule 